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Design Rule Check - PCB1.drc

Design Rule Check - PCB1.drc 8.8 KB
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  1. Protel Design System Design Rule Check
    2. 

  2. PCB File : D:\Altium\bip_Project\PCB1.PcbDoc
    3. 

  3. Date     : 10/6/2024
    4. 

  4. Time     : 3:24:52 PM
    5. 

  5. 

  6. Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
    7. 

  7.    Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad Q2-1(40.073mm,9.331mm) on Multi-Layer And Pad Q2-2(38.803mm,9.458mm) on Multi-Layer 
    8. 

  8.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q2-1(40.073mm,9.331mm) on Multi-Layer And Track (38.803mm,9.458mm)(38.803mm,9.883mm) on Bottom Layer 
    9. 

  9.    Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad Q2-2(38.803mm,9.458mm) on Multi-Layer And Pad Q2-3(37.533mm,9.331mm) on Multi-Layer 
    10. 

  10.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q2-2(38.803mm,9.458mm) on Multi-Layer And Track (35.567mm,7.366mm)(37.533mm,9.331mm) on Bottom Layer 
    11. 

  11.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q2-2(38.803mm,9.458mm) on Multi-Layer And Track (40.073mm,7.044mm)(40.073mm,9.331mm) on Bottom Layer 
    12. 

  12.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q2-3(37.533mm,9.331mm) on Multi-Layer And Track (38.803mm,9.458mm)(38.803mm,9.883mm) on Bottom Layer 
    13. 

  13.    Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad Q4-1(40.073mm,16.329mm) on Multi-Layer And Pad Q4-2(38.803mm,16.456mm) on Multi-Layer 
    14. 

  14.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q4-1(40.073mm,16.329mm) on Multi-Layer And Track (36.209mm,19.05mm)(38.803mm,16.456mm) on Top Layer 
    15. 

  15.    Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad Q4-2(38.803mm,16.456mm) on Multi-Layer And Pad Q4-3(37.533mm,16.329mm) on Multi-Layer 
    16. 

  16.    Violation between Clearance Constraint: (0.188mm < 0.2mm) Between Pad Q4-2(38.803mm,16.456mm) on Multi-Layer And Track (34.163mm,19.699mm)(37.533mm,16.329mm) on Top Layer 
    17. 

  17.    Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad Q4-3(37.533mm,16.329mm) on Multi-Layer And Track (36.209mm,19.05mm)(38.803mm,16.456mm) on Top Layer 
    18. 

  18. Rule Violations :11
    19. 

  19. 

  20. Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
    21. 

  21.    Violation between Short-Circuit Constraint: Between Pad Q2-1(40.073mm,9.331mm) on Multi-Layer And Pad Q2-2(38.803mm,9.458mm) on Multi-Layer Location : [X = 64.888mm][Y = 34.744mm]
    22. 

  22.    Violation between Short-Circuit Constraint: Between Pad Q2-2(38.803mm,9.458mm) on Multi-Layer And Pad Q2-3(37.533mm,9.331mm) on Multi-Layer Location : [X = 63.618mm][Y = 34.744mm]
    23. 

  23.    Violation between Short-Circuit Constraint: Between Pad Q4-1(40.073mm,16.329mm) on Multi-Layer And Pad Q4-2(38.803mm,16.456mm) on Multi-Layer Location : [X = 64.888mm][Y = 41.742mm]
    24. 

  24.    Violation between Short-Circuit Constraint: Between Pad Q4-2(38.803mm,16.456mm) on Multi-Layer And Pad Q4-3(37.533mm,16.329mm) on Multi-Layer Location : [X = 63.618mm][Y = 41.742mm]
    25. 

  25.    Violation between Short-Circuit Constraint: Between Pad Q4-3(37.533mm,16.329mm) on Multi-Layer And Track (36.209mm,19.05mm)(38.803mm,16.456mm) on Top Layer Location : [X = 63.504mm][Y = 42.199mm]
    26. 

  26. Rule Violations :5
    27. 

  27. 

  28. Processing Rule : Un-Routed Net Constraint ( (All) )
    29. 

  29. Rule Violations :0
    30. 

  30. 

  31. Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
    32. 

  32. Rule Violations :0
    33. 

  33. 

  34. Processing Rule : Width Constraint (Min=0.3mm) (Max=0.8mm) (Preferred=0.5mm) (All)
    35. 

  35. Rule Violations :0
    36. 

  36. 

  37. Processing Rule : Width Constraint (Min=0.5mm) (Max=1.6mm) (Preferred=1.2mm) (InNet('GND'))
    38. 

  38. Rule Violations :0
    39. 

  39. 

  40. Processing Rule : Width Constraint (Min=0.5mm) (Max=2mm) (Preferred=1.5mm) (InNet('+24'))
    41. 

  41. Rule Violations :0
    42. 

  42. 

  43. Processing Rule : Routing Topology Rule(Topology=Shortest) (All)
    44. 

  44. Rule Violations :0
    45. 

  45. 

  46. Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
    47. 

  47. Rule Violations :0
    48. 

  48. 

  49. Processing Rule : Hole Size Constraint (Min=0.2mm) (Max=2.54mm) (All)
    50. 

  50.    Violation between Hole Size Constraint: (4.115mm > 2.54mm) Pad Q1-C(57.099mm,35.611mm) on Multi-Layer Actual Hole Size = 4.115mm
    51. 

  51.    Violation between Hole Size Constraint: (4.115mm > 2.54mm) Pad Q1-C/(57.099mm,5.385mm) on Multi-Layer Actual Hole Size = 4.115mm
    52. 

  52. Rule Violations :2
    53. 

  53. 

  54. Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
    55. 

  55. Rule Violations :0
    56. 

  56. 

  57. Processing Rule : Minimum Solder Mask Sliver (Gap=0.001mm) (All),(All)
    58. 

  58. Rule Violations :0
    59. 

  59. 

  60. Processing Rule : Silk To Solder Mask (Clearance=0.001mm) (IsPad),(All)
    61. 

  61.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Arc (38.811mm,2.337mm) on Top Overlay And Pad Q3-C(41.351mm,2.337mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
    62. 

  62.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Arc (38.811mm,2.337mm) on Top Overlay And Pad Q3-E(36.271mm,2.337mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
    63. 

  63.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Arc (38.811mm,2.337mm) on Top Overlay And Pad Q3-E(36.271mm,2.337mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
    64. 

  64.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Arc (38.812mm,2.337mm) on Top Overlay And Pad Q3-C(41.351mm,2.337mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
    65. 

  65.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D4-A(92.532mm,1.702mm) on Multi-Layer And Track (92.532mm,1.487mm)(92.532mm,5.457mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    66. 

  66.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D4-C(92.532mm,17.831mm) on Multi-Layer And Track (92.532mm,14.457mm)(92.532mm,18.427mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    67. 

  67.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D5-A(2.997mm,21.641mm) on Multi-Layer And Track (2.997mm,21.426mm)(2.997mm,25.396mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    68. 

  68.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D5-C(2.997mm,37.77mm) on Multi-Layer And Text "D5" (4.064mm,38.862mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    69. 

  69.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D5-C(2.997mm,37.77mm) on Multi-Layer And Track (2.997mm,34.396mm)(2.997mm,38.366mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    70. 

  70.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D6-A(10.49mm,37.77mm) on Multi-Layer And Track (10.49mm,34.015mm)(10.49mm,37.985mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    71. 

  71.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad D6-C(10.49mm,21.641mm) on Multi-Layer And Track (10.49mm,21.045mm)(10.49mm,25.015mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    72. 

  72.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R4-1(87.307mm,7.937mm) on Multi-Layer And Track (85.402mm,7.937mm)(86.672mm,7.937mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    73. 

  73.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R4-2(75.115mm,7.81mm) on Multi-Layer And Track (76.106mm,7.835mm)(77.071mm,7.835mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    74. 

  74.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R5-1(87.307mm,2.596mm) on Multi-Layer And Track (85.402mm,2.596mm)(86.672mm,2.596mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    75. 

  75.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R5-2(75.115mm,2.469mm) on Multi-Layer And Track (76.106mm,2.494mm)(77.071mm,2.494mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    76. 

  76.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R6-1(86.817mm,13.278mm) on Multi-Layer And Track (84.912mm,13.278mm)(86.182mm,13.278mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    77. 

  77.    Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.001mm) Between Pad R6-2(74.625mm,13.151mm) on Multi-Layer And Track (75.616mm,13.176mm)(76.581mm,13.176mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
    78. 

  78. Rule Violations :17
    79. 

  79. 

  80. Processing Rule : Silk to Silk (Clearance=0.01mm) (All),(All)
    81. 

  81.    Violation between Silk To Silk Clearance Constraint: (Collision < 0.01mm) Between Region (0 hole(s)) Top Overlay And Text "P1" (6.096mm,11.659mm) on Top Overlay Silk Text to Silk Clearance [0mm]
    82. 

  82. Rule Violations :1
    83. 

  83. 

  84. Processing Rule : Net Antennae (Tolerance=0mm) (All)
    85. 

  85. Rule Violations :0
    86. 

  86. 

  87. Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
    88. 

  88. Rule Violations :0
    89. 

  89. 

  90. 

  91. Violations Detected : 36
    92. 

  92. Waived Violations : 0
    93. 

  93. Time Elapsed        : 00:00:00
    94.